1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process and apparatus for depositing dielectric layers on a semiconductor substrate.
2. Background of the Invention
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a semiconductor substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed thereon. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such as described in U.S. Pat. No. 5,362,526. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone near the substrate surface, thereby creating a plasma of highly reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore""s Law), which means that the number of devices that will fit on a chip doubles every two years. Today""s wafer fabrication plants are routinely producing devices having 0.35 xcexcm and even 0.18 xcexcm feature sizes, and tomorrow""s plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low k (dielectric constant less than 4.0) to reduce the capacitive coupling between adjacent metal lines. For example, copper is now being considered as an interconnect material in place of aluminum because copper has a lower resistivity and higher current carrying capacity. However, these materials present new problems for integrated circuit manufacturing processes. For example, many low k dielectric materials are porous and are preferably protected by liner layers to prevent diffusion of metals. Conventional liner layers, such as SiN, have higher dielectric constants, and the combination of low k dielectric layers with high k dielectric liner layers may result in little or no improvement in the overall stack dielectric constant and capacitive coupling.
As shown in FIG. 1A, International Publication Number WO 94/01885 describes a PECVD process for depositing a multi-component dielectric layer wherein a silicon dioxide (SiO2) liner layer 2 is first deposited on a patterned metal layer having metal lines 3 formed on a substrate 4. The liner layer 2 is deposited by reaction of silane (SiH4) and nitrous oxide (N2O). A self-planarizing low k dielectric layer 5 is then deposited on the liner layer 2 by reaction of a silane compound and a peroxide compound. The liner layer 2 is an oxidized silane film that has excellent barrier properties when deposited in a manner which provides a dielectric constant of about 4.5. The dielectric constant of the oxidized silane film can be decreased to about 4.1 by altering process conditions in a manner that decreases barrier properties of the film.
As shown in FIG. 1B, WO 94/01885 further describes an optional SiO2 cap layer 6 that is deposited on the low k dielectric layer 5 by the reaction of silane and N2O. The cap layer 6 is also an oxidized silane film that has excellent barrier properties when deposited in a manner which provides a dielectric constant of about 4.5. Both the liner layer 2 and the cap layer 6 have a dielectric constant greater than 4.0 and the high dielectric constant layers substantially detract from the benefit of the low k dielectric layer.
The benefit of some low k dielectric materials is further compromised by low oxide content which makes the material inadequate as an etch stop layer. Silicon nitride has been the etch stop material of choice for use with low k dielectric materials. However, the silicon nitride disposed between low k dielectric layers is within the fringing field between the interconnects. Silicon nitride has a relatively high dielectric constant (dielectric constant of about 7) compared to the surrounding dielectric, and it has been discovered that the silicon nitride may significantly increase the capacitive coupling between interconnect lines, even when an otherwise low k dielectric material is used as the primary insulator. This may lead to cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the device.
As devices get smaller, liner layers, cap layers, and etch stop layers contribute more to the overall dielectric constant of a multi-component dielectric layer. There remains a need for low k dielectric layers which have excellent barrier properties for use as liner or cap layers. There also remains a need for low k dielectric layers which have sufficient oxide content for use as etch stop layers. Ideally, the low k dielectric layers would be compatible with existing low k dielectric materials and could be deposited in the same chambers as existing low k dielectric materials.
The present invention provides a method and apparatus for deposition of a low dielectric constant layer which is produced by oxidation of an organo silane compound during plasma enhanced chemical vapor deposition. The oxidized organo silane layers have excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers such as porous low k dielectric layers. In addition, the oxidized organo silane layers have can be used as an etch stop layer, as an adhesive layer between different layers, or as an intermetal dielectric layer. A preferred oxidized organ silane layer is produced by reaction of methyl silane, CH3SiH3, and nitrous oxide, N2O.
In a preferred embodiment, a low k dielectric layer is deposited on a patterned metal layer by reaction of an organo silane compound and an oxidizing compound. A self-planarizing dielectric layer is then deposited in the same chamber by reaction of an organo-silane compound and a peroxide bonding compound. The self-planarizing dielectric layer is optionally capped in the same chamber by further reaction of the organo silane compound and the oxidizing compound. The liner and cap layers provide strength to the self-planarizing dielectric layer during annealing of the self-planarizing dielectric layer. After annealing, the liner and cap layers serve as diffusion barriers which protect the self-planarizing dielectric layer.
The present invention further provides an etch stop material which provides a reliable dual damascene structure while minimizing the contribution of the etch stop layer to the capacitive coupling between interconnect lines. In a preferred embodiment, a low k dielectric film, such as an amorphous carbon (xe2x88x9d-C) or amorphous fluorinated carbon (xe2x88x9d-FC) film is used as the etch stop below an intermetal dielectric (IMD). Other low k materials, such as parylene, AF4, BCB, or PAE, or high k materials, such as oxynitride and silicon carbide, may also be used with the etch stop material.
A preferred etch stop process sequence comprises forming a dual damascene structure by depositing a first dielectric layer, such as parylene or a fluorinated silicate glass (FSG) layer, on a substrate, depositing the low k dielectric etch stop of the present invention on the first dielectric layer, patterning the etch stop to define the contacts/vias, depositing a second layer of a dielectric, patterning a resist layer on the second layer of dielectric to define one or more interconnects, and etching the interconnects and contacts/vias. The interconnects are etched down to the etch stop, and then the etching continues past the patterned etch stop to define the contacts/vias , Once the dual damascene structure has been formed, a barrier layer is preferably deposited conformably in the structure prior to filling the structure with copper to isolate the copper from other materials, such as silicon. The upper surface is then planarized using chemical mechanical polishing techniques.
The invention further provides an intermetal dielectric material comprising the low k dielectric film which is deposited on a conventional etch stop such as silicon oxide or silicon nitride. The low k dielectric film can also be deposited as a thin adhesive layer.